Privacy Policy
Disclaimer
Copyright
Contact
Sitemap
   
f-alpha.net » Electronics » Digital Electronics » Counter » Let's go... » Experiment 8 - Asynchronous - Synchronous

Experiment 8 - Asynchronous / Synchronous Counter

Asynchronous counters have a disadvantage. They need time to provide the final result. Especially for long flip-flop chains, the execution time becomes large.

For a flip-flop to compute the result, a propagation delay time of typically 300-500 ns is needed before the result is shown. In an asynchronous counter, the next flip-flop can only to start compute its result after the previous flip-flop has finished computing the resultat. It is said that the result "ripples" through the counter.

Design of an asynchronous counter.

Design of a synchronous counter.

With the synchronous design you shorten the execution time. In a synchronous counter, the input signal is directly connected to all flip-flops and compute the result in parallel...

However, synchronous counter are more complex, as you can see in the next experiments...

Related Topics

Related Experiments

Glossar

Useful Information

Social Media

     

www.f-alpha.net
Login