With a simple NOT gate you prevent that R and S switch simultaneously to 1. The circuit diagram shows you how. Now the former input signal R is always the opposite of the former input S and you are left with a single input, which is renamed to D (for "DATA").
Remember the truth table for the RS latch from experiment 3? With the D latch you prevent not only the undefined state (R=1, S=1), but also the condition in which the last result is stored (R=0, S=0).
In fact, the D latch has lost its memory. Q always follows D!
Convince yourself with the circuit shown.
In the next experiment, you give the circuit its memory back.