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f-alpha.net » Electronics » Digital Electronics » Shift Register » Let's go... » Experiment 6 - Destructive Output

Experiment 6 - The Destructive Output

Look to the state table, where you write the information 1011 into the shift register.

After four clock signals the information is present in the shift register is present. For each subsequent clock signal Clk, the data is shifted further...

DATA Clock (Clk) Q3 Q2 Q1 Q0
1 1 1 0 0 0
1 2 1 1 0 0
0 3 0 1 1 0
1 4 1 0 1 1
0 5 0 1 0 1
0 6 0 0 1 0
0 7 0 0 0 1
0 8 0 0 0 0

State table shift register with destructive output.

After another four clock signals, the information is completely shifted out of the shift register. If you have not stored the information in a different manner in the meantime, it is lost...!

This behavior of a shift register is described by the term "destructive output".

In the next experiments, you will therefore add an additional input...

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