Experiment 5 - The 2-bit Ripple-Carry Adder
An adder, where the carry bit is passed from one digit to the next,
is called a ripple-carry adder.
Thus you can easily build adders of large numbers.
a ripple-carry adder is slow
when it has to add up large numbers.
Consider again the circuit diagram of the 2-bit adder...
Illustration delay of a 2-bit ripple-carry adder.
No logic gate can provide immediate results.
Only after a delay,
the so-called gate delay time τ,
the gate has executed the logic computation.
With the circuit diagram in mind, you can easily make the following
Information about the gate delay times
can be found in the data sheets of the CMOS components.
They are often indicated as
"Propagation Delay Time".
Typical gate delay times are
τ = 60 ns.
The output Q0
is delayed by 1 × τ = 60 ns.
The output Q1
is delayed by 2 × τ = 120 ns.
The Carry-OUT Bit CO
is delayed by 3 × τ = 180 ns.
The full outcome of the 2-bit ripple carry adder is delayed
by three times the gate delay time.
But what about a n-bit ripple-carry adder...?