Experiment 24 - The D Flip-Flop with Asynchronous Inputs

Also an edge-triggered D-type flip-flop can have asynchronous inputs SET and RESET.

Take a look at the circuit shown. You use a C-MOS 4013 with preprogrammed D Flip-Flops.

With the inputs SET and RESET you switch, regardless of the clock signal, Clk the result Q...

• SET sets Q = 1.
• RESET sets Q = 0.

Circuit symbol D flip-flop with asynchronous inputs.

Circuit D flip-flop with asynchronous inputs. (Enlarge)

The input D however has only in conjunction with the clock signal Clk influence on the result Q. Therefore, the input is referred to as synchronous.

In the next experiment you take a look at a JK latch...