Experiment 25 - The JK Latch

In the first experiments on this topic you met the RS and D latch. However, the JK flip-flop you only met as an edge-triggered flip-flop. Why is this...?

With a JK latch, the state J = K = 1 is defined, in contrast to the RS latch. In the circuit diagram shown you can easily follow the signals through the logic gates...

J K Q Q' 0 0 stored 0 1 1 0 1 0 0 1 1 1 toggle Truth table JK latch.

Circuit diagram JK latch.

Caution...! On building the circuit, you immediately encounter a problem...

• With J = K = 1, both LEDs light up with reduced brightness!

Circuit JK latch. (Enlarge)

This is due to a classic timing issue...

The inputs J and K are processed by the logic gates. With even the slightest delay at the output between Q and Q', the JK latch starts to oscillate (typically at a frequency of several MHz...).

This phenomenon is known as a "Race Condition". This has the consequence that the JK latch is in a so-called "metastable state" and starts to oscillate.